Interrupts; Ethernet Mac Programming Model; Dma Controller - Altera Cyclone V Device Handbook

cv_54017
2013.12.30

Interrupts

Interrupts are generated as a result of specific events in the EMAC and external PHY device. The interrupt
status register indicates all conditions which may trigger an interrupt and the interrupt enable register
determines which interrupts can propagate.

Ethernet MAC Programming Model

DMA Controller

The DMA has independent transmit and receive engines, and a CSR space. The transmit engine transfers
data from system memory to the device port or MAC transaction layer (MTL), while the receive engine
transfers data from the device port to the system memory. The controller use descriptors to efficiently move
data from source to destination with minimal Host CPU intervention. The DMA is designed for packet-
oriented data transfers such as frames in Ethernet. The controller can be programmed to interrupt the Host
CPU for situations such as frame transmit and receive transfer completion, and other normal/error conditions.
The DMA and the Host driver communicate through two data structures:
• Control and Status registers (CSR)
• Descriptor lists and data buffers
Descriptor Lists and Data Buffers
The DMA transfers data frames received by the MAC to the receive Buffer in the Host memory, and transmit
data frames from the transmit Buffer in the Host memory. Descriptors that reside in the Host memory act
as pointers to these buffers.
There are two descriptor lists: one for reception and one for transmission. The base address of each list is
written into Register 3 (Receive Descriptor List Address Register) and Register 4 (Transmit Descriptor List
Address Register), respectively. A descriptor list is forward linked (either implicitly or explicitly). The last
descriptor may point back to the first entry to create a ring structure. Explicit chaining of descriptors is
accomplished by setting the second address chained in both receive and transmit descriptors (RDES1[24]
and TDES1[24]). The descriptor lists resides in the Host physical memory address space. Each descriptor
can point to a maximum of two buffers. This enables two buffers to be used, physically addressed, rather
than contiguous buffers in memory.
A data buffer resides in the Host physical memory space, and consists of an entire frame or part of a frame,
but cannot exceed a single frame. Buffers contain only data, buffer status is maintained in the descriptor.
Data chaining refers to frames that span multiple data buffers. However, a single descriptor cannot span
multiple frames. The DMA skips to the next frame buffer when end-of-frame is detected. Data chaining can
be enabled or disabled.
Ethernet Media Access Controller
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Interrupts
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