Altera Cyclone V Device Handbook page 190

6-16
DQS Phase-Shift Circuitry
Figure 6-4: DQS Pins and DLLs in Cyclone V E (A5, A7, and A9), GX (C4, C5, C7, and C9), GT (D5, D7, and
D9) Devices
Altera Corporation
DQS DQS
Pin Pin
DLL
Reference
Clock
Δt Δt
DLL to to
IOE IOE
to to
DLL
IOE IOE
Δt Δt
DLL
Reference
Clock
DQS DQS
Pin Pin
DQS DQS
Pin Pin
DLL
DQS Logic
Blocks Reference
Clock
Δt Δt
to to DLL
IOE IOE
to
IOE
to
IOE
to
IOE
to
IOE
to to
DLL
IOE IOE
Δt Δt
DQS Logic
DLL
Blocks
Reference
Clock
DQS DQS
Pin Pin
External Memory Interfaces in Cyclone V Devices
DQS Logic
Blocks
DQS
Δt
Pin
DQS
Δt
Pin
DQS
Δt
Pin
DQS
Δt
Pin
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CV-52006
2014.01.10