Altera Cyclone V Device Handbook page 569

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2013.12.30
Burst Sizes and Byte Strobes
The ACP improves system performance for hardware accelerators in the FPGA fabric. However, in order
to achieve high levels of performance, you must use the one of the recommended burst types. The other
burst types have significantly lower performance.
Related Information
Recommended Burst Types
Recommended Burst Types
Table 6-3: Recommended Burst Types
Burst Type
Wrapping
Incrementing
Related Information
Burst Sizes and Byte Strobes
Burst Guidelines
Note: If the slave port of the FPGA-to-HPS bridge is not 64 bits wide, you must supply bursts to the FPGA-
to-HPS bridge that are upsized or downsized to the burst types above. For example, if the slave data
width of the FPGA-to-HPS bridge is 32 bits, then bursts of eight beats by 32 bits are required to access
the ACP efficiently.
Caution:
Exclusive and Locked Accesses
The ACP does not support exclusive accesses to coherent memory. The ACP supports exclusive accesses to
non-coherent memory; however, it is important that the exclusive access transaction is not affected by the
upsizing and downsizing logic of the FPGA-to-HPS bridge or the L3 interconnect. If the exclusive access is
broken into multiple transactions due to the sizing logic, the exclusive access bit is cleared by the bridge or
interconnect and the exclusive access fails.
Note: Altera recommends that exclusive accesses bypass the ACP altogether, either through the 32-bit slave
port of the SDRAM controller connected directly to the L3 interconnect or through the FPGA-to-
SDRAM interface.
For more information about the exclusive access support of the SDRAM controller subsystem, refer to the
SDRAM Controller Subsystem chapter in the Cyclone V Device Handbook, Volume 3.
The ACP ID mapper does not support locked accesses. To ensure mutually exclusive access to shared data,
use the exclusive access support built into the SDRAM controller.
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
on page 6-23
Beats
4
4
on page 6-23
If the address and burst size of the transaction to the ACP matches either of the conditions above,
the logic in the MPU assumes the transaction has all its byte strobes set. If the byte strobes are
not all set, then the write does not actually overwrite all the bytes in the word. Instead, the cache
assumes the whole cache line is valid. If this line is dirty (and therefore gets written out to SDRAM),
data corruption might occur.
Width (Bits)
64 64-bit aligned
64 32-bit aligned
Burst Sizes and Byte Strobes
Address Type Byte Strobes
Asserted
Asserted
6-23
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