Differential I/O Termination - Altera Cyclone V Device Handbook

CV-52005
2014.01.10
Figure 5-21: HSTL I/O Standard Termination
This figure shows the details of HSTL I/O termination on the Cyclone V devices.
Termination
External
On-Board
Termination
OCT Transmit
OCT Receive
OCT in
Bidirectional
Pins
Related Information
Dynamic OCT in Cyclone V Devices

Differential I/O Termination

The I/O pins are organized in pairs to support differential I/O standards. Each I/O pin pair can support
differential input and output buffers.
The supported I/O standards such as Differential SSTL-15, Differential SSTL-125, and Differential SSTL-
135 typically do not require external board termination.
Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost.
Dynamic OCT reduces the number of external termination resistors used.
Differential HSTL, SSTL, and HSUL Termination
Differential HSTL, SSTL, and HSUL inputs use LVDS differential input buffers. However, R
only available if the I/O standard is LVDS.
Differential HSTL, SSTL, and HSUL outputs are not true differential outputs. These I/O standards use two
single-ended outputs with the second output programmed as inverted.
I/O Features in Cyclone V Devices
Send Feedback
HSTL Class I
V
TT
50 Ω
50 Ω
V REF
Transmitter
V
TT
Series OCT 50 Ω
50 Ω
50 Ω
V REF
Transmitter
50 Ω
V REF
Transmitter
V
CCIO
Series V REF
OCT 50 Ω
100 Ω
50 Ω
100 Ω
GND
V REF
FPGA
on page 5-40
Receiver Transmitter
Series OCT 25 Ω
Receiver Transmitter
V
FPGA
CCIO
Parallel OCT
100 Ω
100 Ω
GND Receiver Transmitter
V
CCIO
Series
100 Ω OCT 25 Ω
100 Ω
Series
GND
OCT 50 Ω
FPGA FPGA
Differential I/O Termination
HSTL Class II
V
V
TT
TT
50 Ω 50 Ω
50 Ω
V REF
Receiver
V V
TT TT
50 Ω 50 Ω
50 Ω
V REF
Receiver
V
TT
V
CCIO
50 Ω
100 Ω
50 Ω
V REF
100 Ω
GND Receiver
V V
CCIO CCIO
V REF
100 Ω 100 Ω
50 Ω
100 Ω 100 Ω
Series
GND GND
OCT 25 Ω
V REF
FPGA
5-47
FPGA
Parallel OCT
support is
D
Altera Corporation