Ethernet Mac Address Map And Register Definitions; Document Revision History - Altera Cyclone V Device Handbook

17-58

Ethernet MAC Address Map and Register Definitions

example, to control the PPS), then the interrupt generation is over-written with the new mode and new
programmed Target Time register value.
Ethernet MAC Address Map and Register Definitions
The address map and register definitions reside in the hps.html file that accompanies this handbook volume.
Click the link to open the file.
To view the module description and base address, scroll to and click the link for either of the following
module instances:
• emac0
• emac1
To view the register and field descriptions, scroll to and click the register names. The register addresses are
offsets, relative to the base address of each module instance.
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
• Cyclone V SoC HPS Address Map and Register Definitions

Document Revision History

Table 17-21: Document Revision History
Date
December 2013
November 2012
June 2012
Altera Corporation
Version
2013.12.30
1.3
1.2
on page 1-1
Changes
Minor updates.
• Expanded shared memory
block table.
• Added CSEL tables.
• Additional minor updates.
Updated the HPS boot and FPGA
configuration sections.
Ethernet Media Access Controller
cv_54017
2013.12.30
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