Altera Cyclone V Device Handbook page 322

CV-53001
2013.05.06
Block
Receiver Phase Compensation
FIFO
Word Aligner
Parallel data at the input of the receiver PCS loses the word boundary of the upstream transmitter from the
serial-to-parallel conversion in the deserializer. The word aligner receives parallel data from the deserializer
and restores the word boundary based on a pre-defined alignment pattern that must be received during link
synchronization.
The word aligner searches for a pre-defined alignment pattern in the deserialized data to identify the correct
boundary and restores the word boundary during link synchronization. The alignment pattern is pre-defined
for standard serial protocols according to the respective protocol specifications for achieving synchronization.
For proprietary protocol implementations, you can specify a custom word alignment pattern specific to your
application.
In addition to restoring the word boundary, the word aligner implements the following features:
• Synchronization state machine
• Programmable run length violation detection (for all transceiver configurations)
• Receiver polarity inversion (for all transceiver configurations except PCIe)
• Receiver bit reversal (for custom single- and double-width configurations only)
• Receiver byte reversal (for custom double-width configuration only)
The word aligner operates in one of the following three modes:
• Manual alignment
• Automatic synchronization state machine
• Bit-slip
• Deterministic latency state machine
Except for bit-slip mode, after completing word alignment, the deserialized data is synchronized to have the
word alignment pattern at the LSB portion of the aligned data.
Word Aligner Options and Behaviors
The operation mode and alignment pattern length support varies depending on the word aligner
configurations.
Table 1-17: Word Aligner Options and Behaviors
PMA-PCS Interface Width
(bits)
8
Transceiver Architecture in Cyclone V Devices
Send Feedback
• Compensates for the phase difference between the low-speed parallel
clock and the FPGA fabric interface clock when interfacing the receiver
PCS with the FPGA fabric directly or with the PCIe hard IP block
• Supports operation in phase compensation and registered modes
Word Alignment Word Alignment
Mode Pattern Length (bits)
Manual 16
Alignment
Bit-Slip 16
Word Aligner
Functionality
Word Alignment Behavior
User-controlled signal starts the alignment
process. Alignment happens once unless
the signal is reasserted.
User-controlled signal shifts data one bit at
a time.
1-35
Altera Corporation