Hard Memory Controller; Features Of The Hard Memory Controller - Altera Cyclone V Device Handbook

6-30

Hard Memory Controller

Every I/O pin contains one I/O configuration register.
Every DQS pin contains one DQS configuration block in addition to the I/O configuration register.
Figure 6-21: Configuration Block (I/O and DQS)
This figure shows the I/O configuration block and the DQS configuration block circuitry.
Related Information
ALTDQ_DQS2 Megafunction User Guide
Provides details about the I/O and DQS configuration block bit sequence.
Hard Memory Controller
The Cyclone V devices feature dedicated hard memory controllers. You can use the hard memory controllers
for LPDDR2, DDR2, and DDR3 SDRAM interfaces. Compared to the memory controllers implemented
using core logic, the hard memory controllers allow support for higher memory interface frequencies with
shorter latency cycles.
The hard memory controllers use dedicated I/O pins as data, address, command, control, clock, and ground
pins for the SDRAM interface. If you do not use the hard memory controllers, you can use these dedicated
pins as regular I/O pins.
Related Information
Functional Description HPC II Controller chapter, External Memory Interface Handbook
The hard memory controller is functionally similar to the High-Performance Controller II (HPC II).
Functional Description Hard Memory Interface chapter, External Memory Interface Handbook
Provides detailed information about application of the hard memory interface.

Features of the Hard Memory Controller

Table 6-14: Features of the Cyclone V Hard Memory Controller
Feature
Memory Interface
Data Width
Altera Corporation
MSB
datain
update
ena
rankselectread
rankselectwrite
clk
8, 16, and 32 bit data
16 bit data + 8 bit ECC
32 bit data + 8bit ECC
bit2 bit1 bit0
Description
External Memory Interfaces in Cyclone V Devices
dataout
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2014.01.10