Altera Cyclone V Device Handbook page 291

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Transceiver Banks

Figure 1-3: GX/GT Devices with Four or Six Transceiver Channels and Two PCIe HIP Blocks

The PCIe HIP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 4 and Ch 5 of bank GXB_L1.

1. 4-channel device transceiver channels are located on bank L0, and Ch 5 of bank L1.

2. 6-channel device transceiver channels are located on banks L0 and L1.

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PCIe Hard IP

Transceiver Architecture in Cyclone V Devices

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