Altera Cyclone V Device Handbook page 110

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CV-52005
2014.01.10
Table 5-11: Reference Clock Pin for I/O Bank Without Dedicated Reference Clock Pin
Device Variant
Cyclone V E
Cyclone V GX
Cyclone V GT
Cyclone V SE
Cyclone V SX
Cyclone V ST
Guideline: Using LVDS Differential Channels
If you use LVDS channels, adhere to the following guidelines.
LVDS Channel Driving Distance
Each PLL can drive all the LVDS channels in the entire quadrant.
Using Both Corner PLLs
You can use both corner PLLs to drive LVDS channels simultaneously. You can use a corner PLL to drive
all the transmitter channels and the other corner PLL to drive all the receiver channels in the same I/O bank.
Both corner PLLs can drive duplex channels in the same I/O bank if the channels that are driven by each
PLL are not interleaved. You do not require separation between the groups of channels that are driven by
both corner PLLs.
I/O Features in Cyclone V Devices
Send Feedback
Member Code
Data Channel I/O Bank
Banks using bottom
Banks using bottom
A2, A4
Banks using top right
Banks using top left
A5, A9
A7
C4, C5, C9
C3, C7
D5, D9
D7
A2, A4
A5, A6
C2, C4
C5, C6
D5, D6
Guideline: Using LVDS Differential Channels
Reference Clock Pin I/O Bank
right PLL
left PLL
PLL
PLL
3A
5A
5A
3A
5A
5A
3A
5A
3A
3A
5A
3A
5A
5A
5-13
4A
3B
7A
8A
3B
5B
5B
3B
5B
5B
3B
5B
3B
3B
5B
3B
5B
5B
Altera Corporation

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