Resetting The Transmitter With The User-Coded Reset Controller During Device Power-Up - Altera Cyclone V Device Handbook

CV-53003
2013.05.06
Signal Name
rx_cal_busy
pll_locked
rx_is_lockedtoref
rx_is_lockedtodata

Resetting the Transmitter with the User-Coded Reset Controller during Device Power-Up

Follow this reset sequence when designing your User-Coder Reset Controller to ensure a reliable transmitter
initialization after the initial power-up.
The numbers in the figure correspond to the following numbered list, which guides you through the
transmitter reset sequence during device power-up.
1. To reset the transmitter, begin with:
• Assert mgmt_rst_reset at power-up to start the calibration IPs. Hold mgmt_rst_reset active
for a minimum of two reset controller clock cycles.
• Assert and hold pll_powerdown, tx_analogreset, and tx_digitalreset at power-up
to reset the transmitter. You can deassert tx_analogreset at the same time as pll_powerdown.
2. After the transmitter PLL locks, the pll_locked status gets asserted after t
3. After the transmitter calibration completes, the tx_cal_busy status is deasserted. Depending on the
transmitter calibrations, this could happen before or after the pll_locked is asserted.
4. Deassert tx_digitalreset after the gating conditions occur for a minimum duration of t
The gating conditions are:
• pll_powerdown is deasserted
• pll_locked is asserted
• tx_cal_busy is deasserted
The transmitter is out of reset and ready for operation.
Note: During calibration, pll_locked might assert and deassert as the calibration IP runs.
Transceiver Reset Control in Cyclone V Devices
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Resetting the Transmitter with the User-Coded Reset Controller during Device Power-Up
Signal Type
Status
Status
Status
Status
Description
A high on this signal indicates that RX calibration is
active
A high on this signal indicates that the TX PLL is
locked
A high on this signal indicates that the RX CDR is in
the lock to reference (LTR) mode
A high on this signal indicates that the RX CDR is in
the lock to data (LTD) mode
3-7
.
pll_lock
tx_digitalreset
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