Scan Manager Address Map And Register Definitions; Jtag-Ap Register Name Cross Reference Table - Altera Cyclone V Device Handbook

15-8

Scan Manager Address Map and Register Definitions

Before asserting warm reset, the reset manager sends a request to the scan manager. The scan manager stops
the output clock generation and acknowledges the reset manager. The reset manager then issues the warm
reset. To enable this warm reset handshake, configure the scanmgr hsen bit of the reset manager ctrl
register.
Related Information
Reset Manager
For more information about reset handshaking, refer to the Reset Manager chapter.
Scan Manager Address Map and Register Definitions
The address map and register definitions reside in the hps.html file that accompanies this handbook volume.
Click the link to open the file.
To view the module description and base address, scroll to and click the link for the following module
instance:
• scanmgr
To then view the register and field descriptions, scroll to and click the register names. The register addresses
are offsets relative to the base address of each module instance.

JTAG-AP Register Name Cross Reference Table

To improve clarity regarding how Altera uses the JTAG-AP, the ARM register names are changed in the
SoC device. The following table cross references the ARM and Altera names.
Table 15-4: JTAG-AP Register Names
Altera Name
stat
en
fifosinglebyte
fifodoublebyte
fifotriplebyte
fifoquadbyte
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter.
Altera Corporation
on page 3-1
ARM Name
CSW (control/status word)
PSEL
BWFIFO1 for writes, BRFIFO1 for reads
BWFIFO2 for writes, BRFIFO2 for reads
BWFIFO3 for writes, BRFIFO3 for reads
BWFIFO4 for writes, BRFIFO4 for reads
on page 1-1
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2013.12.30
Scan Manager
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