Altera Cyclone V Device Handbook page 514

cv_54004
2013.12.30
Internally, the L3 interconnect is partitioned into the following subswitches:
• L3 main switch
• Main switch used to transfer high-throughput 64-bit data
• Operates at up to half the MPU main clock frequency
• Provides masters with low-latency connectivity to AXI bridges, on-chip memories, SDRAM, and
FPGA manager
• L3 master peripheral switch
• Used to connect memory-mastering peripherals to the main switch
• 32-bit data width
• Operates at up to half the main switch clock frequency
• L3 slave peripheral switch
• Used to provide access to level 3 and 4 slave interfaces for masters of the master peripheral and main
switches
• 32-bit data width
• Five independent L4 buses
The L3 master and slave peripheral switches are fully-connected crossbars. The L3 main switch is a partially-
connected crossbar. The following table shows the connectivity matrix of all the master and slave interfaces
of the L3 main switch.
Table 4-1: L3 Main Switch Connectivity Matrix
L3 Master Peripheral Switch
L2 Cache Master 0
FPGA-to-HPS Bridge
Interconnect
Send Feedback
Masters
Interconnect Block Diagram and System Integration
Connected Slaves
• HPS-to-FPGA Bridge
• ACP ID Mapper Data
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
• L3 Slave Peripheral Switch
• FPGA Manager
• HPS-to-FPGA Bridge
• STM
• Boot ROM
• On-Chip RAM
• L3 Slave Peripheral Switch
• ACP ID Mapper Data
• STM
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
4-3
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