Altera Cyclone V Device Handbook page 92

CV-52004
2014.01.10
Figure 4-35: Clock Switchover Using the
This figure shows a clock switchover waveform controlled by the
sources are functional and
starts the switchover sequence. On the falling edge of
off to prevent clock glitching. On the falling edge of
to
inclk0
currently feeding the PLL.
In automatic override with manual switchover mode, the
Since both clocks are still functional during the manual switch, neither
switchover circuit is positive-edge sensitive, the falling edge of the
circuit to switch back from
repeats.
The
clkswitch
is not available, the state machine waits until the clock is available.
Related Information
Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide
Provides more information about PLL software support in the Quartus II software.
Manual Clock Switchover
In manual clock switchover mode, the
the input clock to the PLL. By default,
A clock switchover event is initiated when the
and being held high for at least three
You must bring the
require another switchover event, you can leave the
switch.
Pulsing the
If and
inclk0
time must be greater than or equal to three of the slower frequency
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
inclk0
as the PLL reference. The
inclk1
inclk0
inclk1
muxout
clkswitch
activeclock
clkbad0
clkbad1
inclk1
signal and automatic switch work only if the clock being switched to is available. If the clock
signal back low again to perform another switchover event. If you do not
clkswitch
signal high for at least three
clkswitch
are different frequencies and are always running, the
inclk1
(Manual) Control
clkswitch
is selected as the reference clock; the
inclk0
inclk1
signal changes to indicate the clock which is
activeclock
To initiate a manual clock switchover event,
both inclk0 and inclk1 must be running when
the clkswitch signal goes high.
activeclock
to . When the
inclk0 clkswitch
signal controls whether
clkswitch
is selected.
inclk0
signal transitions from logic low to logic high,
clkswitch
cycles.
inclk
clkswitch
cycles performs another switchover event.
inclk
Manual Clock Switchover
signal. In this case, both clock
clkswitch
signal goes high, which
clkswitch
, the counter's reference clock,
, the reference clock multiplexer switches from
signal mirrors the
signal goes high. Because the
clkbad
signal does not cause the
clkswitch
signal goes high again, the process
or
inclk0
signal in a logic high state after the initial
clkswitch
and
inclk0 inclk1
4-35
, is gated
muxout
signal.
clkswitch
is selected as
inclk1
signal minimum high
cycles.
Altera Corporation