Altera Cyclone V Device Handbook page 443

TOC-4
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual
AXI Bridges Block Diagram and System Integration.............................................................................5-2
Functional Description of the AXI Bridges..............................................................................................5-3
The Global Programmers View.....................................................................................................5-3
FPGA-to-HPS Bridge......................................................................................................................5-3
HPS-to-FPGA Bridge......................................................................................................................5-7
Lightweight HPS-to-FPGA Bridge..............................................................................................5-10
Clocks and Resets...........................................................................................................................5-13
Data Width Sizing..........................................................................................................................5-14
HPS-FPGA AXI Bridges Address Map and Register Definitions.......................................................5-15
Document Revision History.....................................................................................................................5-15
Cortex-A9 Microprocessor Unit Subsystem.......................................................6-1
Features of the Cortex-A9 MPU Subsystem............................................................................................6-1
Cortex-A9 MPU Subsystem Block Diagram and System Integration..................................................6-2
Cortex-A9 MPU Subsystem with L3 Interconnect.....................................................................6-2
Cortex-A9 MPU Subsystem Internals...........................................................................................6-3
Cortex-A9 MPU Subsystem Components...............................................................................................6-4
Cortex-A9 MPCore..........................................................................................................................6-4
ACP ID Mapper.............................................................................................................................6-24
L2 Cache..........................................................................................................................................6-28
Debugging Modules.......................................................................................................................6-33
Cortex-A9 MPU Subsystem Register Implementation........................................................................6-34
Document Revision History.....................................................................................................................6-35
CoreSight Debug and Trace................................................................................7-1
Features of CoreSight Debug and Trace...................................................................................................7-1
ARM CoreSight Documentation...............................................................................................................7-2
CoreSight Debug and Trace Block Diagram and System Integration..................................................7-3
Functional Description of CoreSight Debug and Trace.........................................................................7-3
Debug Access Port (DAP)..............................................................................................................7-4
System Trace Macrocell (STM)......................................................................................................7-4
Trace Funnel.....................................................................................................................................7-5
Embedded Trace FIFO (ETF)........................................................................................................7-5
AMBA Trace Bus Replicator (Replicator)....................................................................................7-5
Embedded Trace Router (ETR).....................................................................................................7-5
Trace Port Interface Unit (TPIU)..................................................................................................7-5
Embedded Cross Trigger (ECT) System.......................................................................................7-6
Program Trace Macrocell (PTM)..................................................................................................7-9
Altera Corporation