Altera Cyclone V Device Handbook page 93

4-36
Guidelines
Figure 4-36: Manual Clock Switchover Circuitry in Cyclone V PLLs
You can delay the clock switchover action by specifying the switchover delay in the ALTERA_PLL
megafunction. When you specify the switchover delay, the
three cycles plus the number of the delay cycles that has been specified to initiate a clock switchover.
inclk
Related Information
Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide
Provides more information about PLL software support in the Quartus II software.
Guidelines
When implementing clock switchover in Cyclone V PLLs, use the following guidelines:
Automatic clock switchover requires that the
other. Failing to meet this requirement causes the
properly.
When using manual clock switchover, the difference between
(2×). However, differences in frequency, phase, or both, of the two clock sources will likely cause the PLL
to lose lock. Resetting the PLL ensures that you maintain the correct phase relationships between the
input and output clocks.
Both
inclk0
clock switchover event. Failing to meet this requirement causes the clock switchover to not function
properly.
Applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth
PLL. When referencing input clock changes, the low-bandwidth PLL reacts more slowly than a high-
bandwidth PLL. When switchover happens, a low-bandwidth PLL propagates the stopping of the clock
to the output more slowly than a high-bandwidth PLL. However, be aware that the low-bandwidth PLL
also increases lock time.
After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a new
clock. The time it takes for the PLL to relock depends on the PLL configuration.
The phase relationship between the input clock to the PLL and the output clock from the PLL is important
in your design. Assert
signal to go high and be stable before re-enabling the output clocks from the PLL.
The VCO frequency gradually decreases when the current clock is lost and then increases as the VCO
locks on to the backup clock, as shown in the following figure.
Altera Corporation
clkswitch
Clock Switch
Control Logic
inclk0
inclk1
and must be running when the
inclk1
for at least 10 ns after performing a clock switchover. Wait for the locked
areset
N Counter
muxout refclk
clkswitch
and
inclk0 inclk1
and
clkbad[0]
inclk0
clkswitch
Clock Networks and PLLs in Cyclone V Devices
PFD
fbclk
signal must be held high for at least
frequencies be within 20% of each
signals to not function
clkbad[1]
and can be more than 100%
inclk1
signal goes high to initiate the manual
Send Feedback
CV-52004
2014.01.10