Altera Cyclone V Device Handbook page 620

8-20
AXI Port
Table 8-10: Avalon-MM Read Port Signals
Name
reset
clk
read
address
readdata
readdatavalid
waitrequest
burstcount
Related Information
Avalon Interface Specifications
Information about the Avalon-MM protocol
AXI Port
The AXI port uses an AXI-3 interface. Each configured AXI port consists of the signals listed in the following
table. Each AXI interface signal is independent of the other interfaces for all signals, including clock and
reset.
Table 8-11: AXI Port Signals
Name
ARESETn
ACLK
Altera Corporation
Bits
1
1
1
32
32, 64, 128, or 256
1
1
11
Bits
1
1
Direction
In Reset
In Clock
In Indicates read transaction
In Address of the transaction
Out Read data return
Out Flags valid cycles for read data return
Out Indicates the need for additional cycles to
complete a transaction. Needed for read
operations when delay is needed to accept the
read command.
In Transaction burst length
Direction
In Reset
In Clock
cv_54008
2013.12.30
Function
Function
SDRAM Controller Subsystem
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