Altera Cyclone V Device Handbook page 357

CV-53002
2013.05.06
The FPGA fabric-transceiver interface clocks consist of clock signals from the FPGA fabric to the transceiver
blocks and clock signals from the transceiver blocks to the FPGA fabric. These clock resources use the clock
networks in the FPGA core, including the global (GCLK), regional (RCLK), and periphery (PCLK) clock
networks.
The FPGA fabric transceiver interface clocks can be subdivided into the following three categories:
• Input reference clocks—Can be an FPGA fabric transceiver interface clock. This may occur when the
FPGA fabric-transceiver interface clock is forwarded to the FPGA fabric, where it can then clock logic.
• Transceiver datapath interface clocks—Used to transfer data, control, and status signals between the
FPGA fabric and the transceiver channels. The transceiver channel forwards the tx_clkout signal to
the FPGA fabric to clock the data and control signals into the transmitter. The transceiver channel also
forwards the recovered rx_clkout clock (in configurations without the rate matcher) or the
tx_clkout clock (in configurations with the rate matcher) to the FPGA fabric to clock the data and
status signals from the receiver into the FPGA fabric.
• Other transceiver clocks—The following transceiver clocks form a part of the FPGA fabric transceiver
interface clocks:
• mgmt_clk—Avalon
ration, and calibration
• fixed_clk—the 125 MHz fixed-rate clock used in the PCIe (PIPE) receiver detect circuitry
Transceiver Clocking in Cyclone V Devices
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-MM interface clock used for controlling the transceivers, dynamic reconfigu-
FPGA Fabric Transceiver Interface Clocking
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