Debug Access Port (Dap); System Trace Macrocell (Stm) - Altera Cyclone V Device Handbook

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Debug Access Port (DAP)

CoreSight technology provides the following features:
• Cross-trigger support between SoC subsystems
• High data compression
• Multisource trace in a single stream
• Standard programming models for standard tool support
Related Information
Info center
You can download the documents from the ARM info center website.
Debug Access Port (DAP)
The DAP provides the necessary ports for a host debugger to connect to and communicate with the HPS
through a JTAG interface connected to dedicated HPS pins that is independent of the JTAG for the FPGA.
The JTAG interface provided with the DAP allows a host debugger to access various modules inside the
HPS. Additionally, a debug monitor executing on either processor can access different HPS components by
interfacing with the system Advanced Microcontroller Bus Architecture (AMBA
™
Bus (APB ) slave port of the DAP. The system APB slave port occupies 2 MB of address space in the HPS.
Both the JTAG port and system APB port have access to the debug APB master port of the DAP. As shown
in Figure 7-1, all CoreSight components are connected to the debug APB.
A host debugger can access any HPS memory-mapped resource in the system via the DAP system master
port. Requests made over the DAP system master port are impacted by reads and writes to peripheral registers.
Note: The HPS JTAG interface does not support boundary scan tests (BST). To perform boundary scan
testing on HPS I/Os, use the FPGA JTAG pins.
Related Information
Info center
For more information, refer to the CoreSight Components Technical Reference Manual on the ARM info
center website.

System Trace Macrocell (STM)

The STM allows messages to be injected into the trace stream for delivery to the host debugger receiving the
trace data. These messages can be sent via stimulus ports or the hardware event interface. The STM allows
the messages to be time stamped.
The STM provides an AMBA Advanced eXtensible Interface (AXI
events. The interface can be accessed by the MPU subsystem, direct memory access (DMA) controller, and
masters implemented as soft logic in the FPGA fabric via the FPGA-to-HPS bridge. The AXI slave interface
supports three address segments, where each address segment is 16 MB and each segment supports up to
65536 channels. Each channel occupies 256 bytes of address space.
The STM also provides 32 hardware event pins. The higher-order 28 pins (31:4) are connected to the FPGA
fabric, allowing logic inside FPGA to insert messages into the trace stream. When the STM detects a rising
edge on an event pin, a message identifying the event is inserted into the stream. The lower four event pins
(3:0) are connected to csCTI.
Altera Corporation
®
) Advanced Peripheral
™
) slave interface used to create trace
CoreSight Debug and Trace
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2013.12.30