Altera Cyclone V Device Handbook page 502

3-6
Module Reset Signals
Checkmarks in the Cold Reset, Warm Reset, and Debug Reset columns denote reset signals asserted by each
type of reset. For example, writing a 1 to the swwarmrstreq bit in the ctrl register resets all the modules
that have a checkmark in the Warm Reset column.
Checkmarks in the Software Deassert column denote reset signals that are left asserted by the reset manager.
To activate the related modules, software can deassert these reset signals as needed by writing to the following
reset manager registers:
• MPU module reset register (mpumodrst)
• Peripheral module reset register (permodrst)
• Peripheral 2 module reset register (per2modrst)
• Bridge module reset register (brgmodrst)
Table 3-3: MPU Group, Generated Module Resets
Module Reset Signal
mpu_cpu_rst_n[0]
mpu_cpu_rst_n[1]
mpu_wd_rst_n
mpu_scu_periph_rst_n
mpu_l2_rst_n
Table 3-4: PER Group, Generated Module Resets
Module Reset Signal
emac_rst_n[1:0]
usb_rst_n[1:0]
nand_flash_rst_n
qspi_flash_rst_n
watchdog_rst_n[1:0]
osc1_timer_rst_n[1:0]
sp_timer_rst_n[1:0]
i2c_rst_n[3:0]
uart_rst_n[1:0]
Altera Corporation
Description
Resets each processor in the
MPU
Resets each processor in the
MPU
Resets both per-processor
watchdogs in the MPU
Resets Snoop Control Unit
(SCU) and peripherals
Level 2 (L2) cache reset
Description
Resets each EMAC
Resets each USB
Resets NAND flash controller
Resets quad SPI flash
controller
Resets each system watchdog
timer
Resets each OSC1 timer
Resets each SP timer
Resets each I2C controller
Resets each UART
Reset Cold Warm
Domain Reset Reset
System X X
System X X
System X X
System X X
System X X
Reset Cold Warm
Domain Reset Reset
System X X
System X X
System X X
System X X
System X X
System X X
System X X
System X X
System X X
cv_54003
2013.12.30
Debug Software
Reset Deassert
X
Debug Software
Reset Deassert
X
X
X
X
X
X
X
X
X
Reset Manager
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