Altera Cyclone V Device Handbook page 846

16-50
Aligned Burst Size Unaligned MFIFO Buffer
DMAST ; shown as g in the figure below
DMAEND
Figure 16-30: Unaligned to Aligned with Excess Initial Load
The first DMALD instruction loads five bursts of data to enable the DMAC to execute the first DMAST.
After the first DMALD, the subsequent DMALDs are not aligned to the source burst size, for example the
second DMALD reads from address 0x1028. After the loop, the final two DMALDs read the data required to
satisfy the final DMAST.
Note: The DMALD shown as f does not increase the MFIFO buffer usage because it loads four bytes into an
MFIFO buffer entry that the DMAC has already allocated to this channel.
This example has a static requirement of one MFIFO buffer entry and a dynamic requirement of four MFIFO
buffer entries.
Related Information
Unaligned Source Address to Aligned Destination Address
Aligned Burst Size Unaligned MFIFO Buffer
In this program, the destination address, which is narrower than the MFIFO buffer width, aligns with the
burst size, but does not align with the MFIFO buffer width.
DMAMOV CCR, SB4 SS32 DB4 DS32
DMAMOV SAR, 0x1000
DMAMOV DAR, 0x4004
DMALP 16
DMALD ; shown as a in the figure below
DMAST ; shown as b in the figure below
Altera Corporation
a c c c n
5
e
4
1
b d d d
0
Data from
DMALD
7
a a a a a a a a
a a a a a a a a
Data for
a a a a a a a a
first DMAST
a a a a a a a a
c c c c a a a a
f
c c c c c c c c
c c c c c c c c
Data for
c c c c c c c c
14x DMAST
g
e e e e c
e e e e e e e e
Data for
e e e e e e e e
last DMAST
f f
on page 16-48
DMALD
0
c c c
n n n n
f f e e e e
DMAST
DMA Controller
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2013.12.30