Error Detection Frequency; Crc Calculation Time - Altera Cyclone V Device Handbook

CV-52008
2013.11.12
Variant
Cyclone V GT
Cyclone V SE
Cyclone V SX
Cyclone V ST

Error Detection Frequency

You can control the speed of the error detection process by setting the division factor of the clock frequency
in the Quartus II software. The divisor is 2
The speed of the error detection process for each data frame is determined by the following equation:
Figure 8-1: Error Detection Frequency Equation
Table 8-2: Error Detection Frequency Range for Cyclone V Devices
The following table lists the frequencies and valid values of n.
Internal Oscillator Frequency
100 MHz

CRC Calculation Time

The time taken by the error detection circuitry to calculate the CRC for each frame is determined by the
device in use and the frequency of the error detection clock.
You can calculate the minimum and maximum time for any number of divisor based on the following
formula:
Maximum time (n) = 2^(n-8) * maximum time
Minimum time (n) = 2^n * minimum time
where the range of n is from 0 to 8.
SEU Mitigation for Cyclone V Devices
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Member Code
D5
D7
D9
A2
A4
A5
A6
C4
C5
C6
D5
D6
n
, where n can be any value listed in the following table.
Error Detection Frequency =
Error Detection Frequency
Maximum Minimum
100 MHz 390 kHz
Error Detection Frequency
Timing Interval (µs)
Internal Oscillator Frequency
n
2
n
0, 1, 2, 3, 4, 5, 6, 7, 8
8-3
1.79
2.33
3.23
1.77
1.77
2.31
2.31
1.77
2.31
2.31
2.31
2.31
Divisor Range
1 – 256
Altera Corporation