Clocks; Resets - Altera Cyclone V Device Handbook

cv_54018
2013.12.30
Port Name
ulpi_dir
ulpi_nxt
ulpi_stp
ulpi_data[7:0]

Clocks

Table 18-3: USB OTG Controller Clock Inputs
All clocks must be operational when reset is released. No special handling is required on the clocks.
Clock Signal
usb_mp_clk
usb0_ulpi_clk
usb1_ulpi_clk

Resets

The USB OTG controller can be reset either through the hardware reset input or through software.
Reset Requirements
There must be a minimum of 12 cycles on the ulpi_clk clock before the controller is taken out of reset.
During reset, the USB OTG controller asserts the ulpi_stp signal. The PHY outputs a clock when it sees
the ulpi_stp signal asserted. However, if the pin multiplexers are not programmed, the PHY does not
see the ulpi_stp signal. As a result, the ulpi_clk clock signal does not arrive at the USB OTG controller.
USB 2.0 OTG Controller
Send Feedback
Bit Width Direction
1 Input
1 Input
1 Output
8 Bidirectional
Frequency
60 – 200 MHz Drives the master and slave interfaces, DMA controller, and internal
FIFO buffers
60 MHz ULPI reference clock for usb0 from external ULPI PHY I/O pin
60 MHz ULPI reference clock for usb1 from external ULPI PHY I/O pin
Description
ULPI Data Bus Control
1 The PHY has data to transfer to the USB OTG
controller.
0 The PHY does not have data to transfer.
ULPI Next Data Control
Indicates that the PHY has accepted the current byte
from the USB OTG controller. When the PHY is
transmitting, this signal indicates that a new byte is
available for the controller.
ULPI Stop Data Control
The controller drives this signal high to indicate the
end of its data stream. The controller can also drive
this signal high to request data from the PHY.
Bidirectional data bus. Driven low by the controller
during idle.
Functional Usage
18-9
Clocks
Altera Corporation