Document Revision History - Altera Cyclone V Device Handbook

2-28

Document Revision History

To clock six identical channels with a single clock, perform these steps:
• Instantiate the rx_coreclkin port for all the identical receiver channels (rx_coreclkin[5:0]).
• Connect rx_clkout[4] to the rx_coreclkin[5:0] ports.
• Connect rx_clkout[4] to the receiver data and control logic for all six channels.
Note: Resetting or powering down channel 4 leads to a loss of the clock for all six channels.
The common clock must have a 0 ppm difference for the write side of the RX phase compensation FIFO of
all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending on
whether the common clock is faster or slower, respectively.
You can drive the 0 ppm common clock driver from one of the following sources:
• tx_clkout of any channel in non-bonded receiver channel configurations with the rate matcher
• rx_clkout of any channel in non-bonded receiver channel configurations without the rate matcher
• tx_clkout[0] in bonded receiver channel configurations
• Dedicated refclk pins
Note: The Quartus II software does not allow gated clocks or clocks generated in the FPGA logic to drive
the rx_coreclkin ports.
Note: You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference
because it allows you to use external pins, such as dedicated refclk pins.
Document Revision History
The table below lists the revision history for this chapter.
Table 2-10: Document Revision History
Date
May 2013
November 2012
June 2012
October 2011
Altera Corporation
Version
2013.05.06 • Updated Content for Quartus II software version 13.0
• Updated figure "Input Reference Clock Sources for Transceiver
Channels"
• Added a section on "Dual-Purpose RX/refclk Pins".
• Added link to the known document issues in the Knowledge Base.
2012.11.19 • Reorganized content and updated template.
• Updated for the Quartus II software version 12.1.
1.1 Minor editorial changes.
1.0 Initial release.
Changes
Transceiver Clocking in Cyclone V Devices
CV-53002
2013.05.06
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