Altera Cyclone V Device Handbook page 862

cv_54017
2013.12.30
The EMAC component provides a hardware assisted implementation of the IEEE 1588 protocol. Hardware
support is for timestamp maintenance. Timestamps are updated when receiving any frame on the PHY
interface and the receive descriptor is updated with this value. Timestamps are also updated when the SFD
of a frame is transmitted and updates the transmit descriptor accordingly.
For details about the IEEE 1588-2002 standard, refer to IEEE Standard 1588-2002 - IEEE Standard for a
Precision Clock Synchronization Protocol for Networked Measurement and Control Systems, available on the
IEEE Standards Association website (http://standards.ieee.org).
Related Information
IEEE Standards Association website
For more information on the IEEE standards, refer to the IEEE Standards Association website.
EMAC to FPGA IEEE1588 Timestamp Interface
Table 17-4: EMAC to FPGA IEEE1588 Timestamp Interface
Signal Name
f2h_emac_ptp_ref_clk
ptp_pps_o
ptp_aux_ts_trig_i
Reference Timing Source
To get a snapshot of the time, the EMAC takes the reference clock input and uses it to generate the reference
time (64-bit) internally and capture timestamps.
Ethernet Media Access Controller
Send Feedback
EMAC to FPGA IEEE1588 Timestamp Interface
In/Out Width
In 1 Timestamp PTP Clock reference from the
FPGA. Used as PTP clock reference for each
EMAC when the FPGA has implemented
timestamp capture interface. Common for all
three EMACs.
Out 1 Pulse Per Second. This signal is asserted based
on the PPS mode selected in the Register 459
(PPS Control Register). Otherwise, this pulse
signal is asserted every time the seconds counter
is incremented.
Synchronous to f2h_emac_f2hptp_ref_clk. Can
only be sampled if FPGA clock is used as
timestamp reference.
In 1 Auxiliary Timestamp Trigger.
This signal is asserted to take an auxiliary
snapshot of the time and store it in the 4-deep
auxiliary timestamp FIFO.
A rising edge on this port is used to trigger the
auxiliary snapshot. The signal is synchronized
internally with clk_ptp_ref_i which results in
an additional delay of three cycles.
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Description
17-13
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