Altera Cyclone V Device Handbook page 470

1-14
SDRAM Address Space
Identifier
PERIPH
LWFPGASLAVES
Related Information
MPU Address Space
For specific details, refer to the "MPU Address Space" section.
SDRAM Address Space
The SDRAM address space is up to 4 GB. The entire address space can be accessed through the FPGA-to-
HPS SDRAM interface from the FPGA fabric. The total amount of SDRAM addressable from the other
address spaces varies.
Related Information
• MPU Address Space
For specific details, refer to the "MPU Address Space" section.
• L3 Address Space
For specific details, refer to the "L3 Address Space" section.
MPU Address Space
The MPU address space is 4 GB and applies to addresses generated inside the MPU.
The MPU address space contains the following regions:
• The SDRAM window region provides access to a large, configurable portion of the 4 GB SDRAM address
space.
• The MPU L2 cache controller contains a master connected to the L3 interconnect and a master connected
to the SDRAM.
• The address filtering start and end registers in the L2 cache controller define the SDRAM window
boundaries.
• The boundaries are megabyte-aligned.
• Addresses within the boundaries route to the SDRAM master.
• Addresses outside the boundaries route to the L3 interconnect master.
As shown in the HPS Address Space Relationship diagram, the reset values of the SDRAM window boundaries
are shown. By default, processor accesses to locations between 0x100000 (1 MB) to 0xC0000000 (3 GB) are
made to the SDRAM controller, accesses to all other locations are made to the L3 interconnect. Addresses
in the SDRAM window match addresses in the SDRAM address space. Thus, the lowest 1 MB of the SDRAM
is not visible to the MPU unless the L2 address filter start register is set to 0. For more information about
L2 address filtering, refer to the Cortex A9 MPU System chapter in volume 3 of the Cyclone
Overview.
The boot region is 1 MB starting at address 0x0 and is visible to the MPU only when the L2 address filter
start register is set to 0x100000. The L3 interconnect Global Programmers View (GPV) remap control register
determines if the boot region is mapped to the on-chip RAM or the boot ROM. For information about the
(1)
This space is part of the "PERIPH" space.
Altera Corporation
Region Name
Peripheral
(1)
Lightweight FPGA slaves
on page 1-14
on page 1-14
on page 1-15
Base Address
0xFC000000
0xFF200000
Introduction to Cyclone V Hard Processor System (HPS)
cv_54001
2013.12.30
Size
64 MB
2 MB
®
V Device
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