Altera Cyclone V Device Handbook page 698

11-20
Single Block Data
If the bytcnt register is written with a nonzero value and the send_auto_stop bit in the cmd register
is set to 1, the STOP command is internally generated and loaded in the command path when the end bit
of the STOP command occurs after the last byte of the stream write transfer matches. This data transfer can
also terminate if the host issues a STOP command before all the data bytes are transferred to the card bus.
Single Block Data
If the transfer_mode bit in the cmd register is set to 0 and the bytcnt register value is equal to the
value of the block_size register, a single-block write-data transfer occurs. The data transmit state machine
sends data in a single block, where the number of bytes equals the block size, including the internally-generated
16-term CRC (CRC-16).
If the ctype register is set for a 1-bit, 4-bit, or 8-bit data transfer, the data is transmitted on 1, 4, or 8 data
lines, respectively, and CRC-16 is separately generated and transmitted for 1, 4, or 8 data lines, respectively.
After a single data block is transmitted, the data transmit state machine receives the CRC status from the
card and signals a data transfer to the BIU. This happens when the dto bit in the rintsts register is set
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to 1.
If a negative CRC status is received from the card, the data path signals a data CRC error to the BIU by
setting the dcrc bit in the rintsts register.
Additionally, if the start bit of the CRC status is not received by two clock cycles after the end of the data
block, a CRC status start-bit error (SBE) is signaled to the BIU by setting the sbe bit in the rintsts
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register.
Multiple Block Data
A multiple-block write-data transfer occurs if the transfer_mode bit in the cmd register is set to 0 and
the value in the bytcnt register is not equal to the value of the block_size register. The data transmit
state machine sends data in blocks, where the number of bytes in a block equals the block size, including the
internally-generated CRC-16 value.
If the ctype register is set to 1-bit, 4-bit, or 8-bit data transfer, the data is transmitted on 1, 4, or 8 data
lines, respectively, and CRC-16 is separately generated and transmitted on 1, 4, or 8 data lines, respectively.
After one data block is transmitted, the data transmit state machine receives the CRC status from the card.
If the remaining byte count becomes 0, the data path signals to the BIU that the data transfer is done. This
happens when the dto bit in the rintsts register is set to 1.
If the remaining data bytes are greater than zero, the data path state machine starts to transmit another data
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block.
If a negative CRC status is received from the card, the data path signals a data CRC error to the BIU by
setting the dcrc bit in the rintsts register, and continues further data transmission until all the bytes
are transmitted.
If the CRC status start bit is not received by two clock cycles after the end of a data block, a CRC status SBE
is signaled to the BIU by setting the ebe bit in the rintsts register and further data transfer is terminated.
If the send_auto_stop bit is set to 1 in the cmd register, the SD/SDIO STOP command is internally
generated during the transfer of the last data block, where no extra bytes are transferred to the card. The
end bit of the STOP command might not exactly match the end bit of the CRC status in the last data block.
If the block size is less than 4, 16, or 32 for card data widths of 1 bit, 4 bits, or 8 bits, respectively, the data
transmit state machine terminates the data transfer when all the data is transferred, at which time the
internally-generated STOP command is loaded in the command path.
Altera Corporation
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cv_54011
2013.12.30
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SD/MMC Controller
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