Pll Locations In Cyclone V Devices - Altera Cyclone V Device Handbook

CV-52004
2014.01.10
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Figure 4-15: PLL Physical Counters Orientation for Cyclone V Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
PLL

PLL Locations in Cyclone V Devices

Cyclone V devices provide a PLL for each group of three transceiver channels. These PLLs are located in a
strip, where the strip refers to an area in the FPGA.
For the PLL in the strip, only PLL counter
PLL counter
The total number of PLLs in the Cyclone V devices includes the PLLs in the PLL strip. However, the
transceivers can only use the PLLs located in the strip.
The following figures show the physical locations of the fractional PLLs. Every index represents one fractional
PLL in the device. The physical locations of the fractional PLLs correspond to the coordinates in the Quartus II
Chip Planner.
Figure 4-16: PLL Locations for Cyclone V E A2 and A4 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Clock Networks and PLLs in Cyclone V Devices
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Physical Counter C0
Physical Counter C1
Physical Counter C8
are used for supporting high-speed requirement of HSSI applications.
C[0..3]
FRACTIONALPLL_X0_Y38
FRACTIONALPLL_X0_Y1
Physical Counter
C0 to C8
PLL
(Up-to-Down
Sequence)
of the strip fractional PLLs are used in a clock network.
C[4..8]
CLK[8..11][p,n]
Pins
CLK[10,11]
4 Logical Clocks
4
FRACTIONALPLL_X54_Y38
4
FRACTIONALPLL_X54_Y1
4 Logical Clocks
CLK[2,3]
Pins
CLK[0..3][p,n]
PLL Locations in Cyclone V Devices
Physical Counter C8
Physical Counter C7
Physical Counter C0
2 Logical Clocks
Logical
Clocks
3 1
Pins
CLK[6][p,n]
2 Logical Clocks
4-17
Physical Counter
C8 to C0
(Down-to-Up
Sequence)
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