Altera Cyclone V Device Handbook page 882

cv_54017
2013.12.30
Figure 17-9: Receive DMA Operation
Set Descriptor
If software has enabled timestamping through CSR, when a valid timestamp value is not available
for the frame (for example, because the receive FIFO buffer was full before the timestamp could be
written to it), the DMA writes all-ones to RDES2 and RDES3. Otherwise (that is, if timestamping
is not enabled), the RDES2 and RDES3 remain unchanged.
Related Information
Receive Descriptor
Ethernet Media Access Controller
Send Feedback
Own Bit
no no
Flush
Set For Next
Disabled?
Descriptor?
yes yes
Close RDES0 As
Intermediate Descriptor
Error
Start
Rx DMA
Poll Demand/
New Frame Available
(Re-)Fetch Next
Descriptor
Rx DMA
Error?
Suspended
no
yes
Frame
no
Transfer
Own Bit Set?
Complete?
no yes
yes Flush
Frame Data
Disabled?
Available?
no yes
Flush the Write Data
Remaining Frame to Buffer(s)
no
Fetch Next
Error?
Descriptor
Error?
no
Frame
no yes
Timestamp
Transfer
Present?
Complete?
no
Close RDES0 As
Last Descriptor
Error?
yes
†
Reception
Start
Stop
Rx DMA
yes
no
Wait for Frame
Data
yes
yes
Write Timestamp
to RDES2 & RDES3
no
Error?
no
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