Altera Cyclone V Device Handbook page 62

CV-52004
2014.01.10
internal logic within a given quadrant can also drive RCLKs to create internally generated regional clocks
and other high fan-out control signals.
Figure 4-3: RCLK Networks in Cyclone V E, GX, and GT Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Figure 4-4: RCLK Networks in Cyclone V SE, SX, and ST Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Periphery Clock Networks
Cyclone V devices provide only horizontal PCLKs from the left periphery.
Clock outputs from the programmable logic device (PLD)-transceiver interface clocks, horizontal I/O pins,
and internal logic can drive the PCLK networks.
Clock Networks and PLLs in Cyclone V Devices
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CLK[8..11][p,n]
RCLK[0..9]
RCLK[40..45]
RCLK[64..69]
Q1 Q2
Q4 Q3
RCLK[82..87]
RCLK[58..63]
RCLK[30..39]
CLK[0..3][p,n]
CLK[6,7][p,n]
RCLK[0..9]
RCLK[40..45]
RCLK[64..69]
Q1 Q2
Q4 Q3
RCLK[82..87]
RCLK[58..63]
RCLK[30..39]
CLK[0..3][p,n]
RCLK[10..19]
RCLK[46..51]
RCLK[70..75]
RCLK[76..81]
RCLK[52..57]
RCLK[20..29]
RCLK[70..75]
RCLK[76..81]
RCLK[52..57]
RCLK[20..29]
Periphery Clock Networks
For Cyclone V E A2
and A4 devices, and
Cyclone V GX C3 device,
only CLK[6][p,n] pins are
available.
RCLK network is not
available in quadrant 2 for
Cyclone V SE A5 and A6
devices, and Cyclone V ST
D5 and D6 devices.
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