Dma Controller Operation - Altera Cyclone V Device Handbook

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Example: Slave Selection Software Flow for SPI Slave
Example: Slave Selection Software Flow for SPI Slave
1. If the SPI slave is enabled, disable it by writing 0 to SSIENR.
2. Write CTRLR0 to match the required transfer.
3. Write TXFTLR and RXFTLR to set FIFO buffer threshold levels.
4. Write IMR register to set interrupt masks.
5. Write SSIENR register bit[0] to logic '1' to enable SPI slave.
6. If the SPI slave transmits data, write data into TX FIFO buffer. Note all other SPI slaves are disabled
(SSIENR = 0) and therefore will not respond to an active level on their ss_in_n port.
The FIFO buffer depth (FIFO_DEPTH) for both the RX and TX buffers in the SPI controller is 256 entries.

DMA Controller Operation

To enable the DMA controller interface on the SPI controller, you must write the DMA Control Register
(DMACR). Writing a 1 to the TDMAE bit field of DMACR register enables the SPI controller transmit
handshaking interface. Writing a 1 to the RDMAE bit field of the DMACR register enables the SPI controller
receive handshaking.†
Related Information
DMA Controller
For details about the DMA controller, refer to the DMA Controller chapter.
DMA Operation
For more information about the DMA operation, refer to the ARM DMA chapter.
Related Information
DMA Controller
For details about the DMA controller, refer to the DMA Controller chapter.
Transmit FIFO Buffer Underflow
During SPI serial transfers, transmit FIFO buffer requests are made to the DMA Controller whenever the
number of entries in the transmit FIFO buffer is less or equal to the value in DMA Transmit Data Level
Register (DMATDLR); also known as the watermark level. The DMA Controller responds by writing a burst
of data to the transmit FIFO buffer, of length specified as DMA burst length.†
Note: Data should be fetched from the DMA often enough for the transmit FIFO buffer to perform serial
transfers continuously, that is, when the FIFO buffer begins to empty, another DMA request should
be triggered. Otherwise, the FIFO buffer will run out of data (underflow). To prevent this condition,
you must set the watermark level correctly.†
Related Information
DMA Controller
For details about the DMA burst length microcode setup, refer to the DMA Controller chapter.
Transmit Watermark Level
Consider the example where the assumption is made: †
DMA burst length = FIFO_DEPTH - DMATDLR
Altera Corporation
on page 16-1
on page 16-1
on page 16-1
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2013.12.30
SPI Controller
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