Altera Cyclone V Device Handbook page 387

CV-53004
2013.10.17
PIPE Interface
In a PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status
signals between the PHY-MAC layer and the transceiver channel PCS and PMA blocks.
Note: The PIPE interface block is used in a PIPE configuration and cannot be bypassed.
In addition to transferring data, control, and status signals between the PHY-MAC layer and the transceiver,
the PIPE interface block implements the following functions that are required in a PCIe-compliant physical
layer device:
• Forces the transmitter buffer into an electrical idle state
• Initiates the receiver detect sequence
• Controls the 8B/10B encoder disparity when transmitting a compliance pattern
• Manages the PCIe power states (Electrical Idle only)
• Indicates the completion of various PHY functions, such as receiver detection and power state transitions
on the pipe_phystatus signal
• Encodes the receiver status and error conditions on the pipe_rxstatus[2:0] signal, as specified
in the PCIe specification
Transmitter Electrical Idle Generation
The PIPE interface block places the channel transmitter buffer in an electrical idle state when the electrical
idle input signal is asserted.
During electrical idle, the transmitter buffer differential and common configuration output voltage levels
are compliant to the PCIe Base Specification 2.1 for the PCIe Gen2 data rate.
The PCIe specification requires that the transmitter buffer be placed in electrical idle in certain power states.
Power State Management
The PCIe specification defines four power states: P0, P0s, P1, and P2.
The physical layer device must support these power states to minimize power consumption:
• P0 is the normal operating state during which packet data is transferred on the PCIe link.
• P0s, P1, and P2 are low-power states into which the physical layer must transition as directed by the
PHY-MAC layer to minimize power consumption.
The PIPE interface in the transceivers provides an input port for each transceiver channel configured in a
PIPE configuration.
Note: When transitioning from the P0 power state to lower power states (P0s, P1, and P2), the PCIe
specification requires that the physical layer device implements power saving measures. The
transceivers do not implement these power saving measures except to place the transmitter buffer
in electrical idle in the lower power states.
8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and Status State Machine
(LTSSM) enters a polling compliance substate. The polling compliance substate assesses if the transmitter
is electrically compliant with the PCIe voltage and timing specifications.
Transceiver Protocol Configurations in Cyclone V Devices
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PIPE Interface
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