Altera Cyclone V Device Handbook page 390

4-8
PCIe Supported Configurations and Placement Guidelines
Figure 4-5: 12 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x2 and x4 Channel Placement
Figure 4-6: 12 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x1 Channel Placement
Altera Corporation
Transceiver Bank
Ch5
Ch4
Ch3
Ch2
PCIe x4
Ch1
PCIe x2
Ch0
Transceiver Bank
Ch5
Ch4
Ch3
Ch2
PCIe x4
Ch1
PCIe x2
Ch0
Transceiver Bank
Ch5
Ch4
Ch3
Ch2
Ch1
CMU PLL
PCIe x1
Ch0
Master
Transceiver Bank
Ch5
Ch4
Ch3
Ch2
Ch1
CMU PLL
PCIe x1
Ch0
Master
CMU PLL
PCIe
Hard IP
Master
CMU PLL
PCIe
Hard IP
Master
PCIe
Hard IP
PCIe
Hard IP
Transceiver Protocol Configurations in Cyclone V Devices
CV-53004
2013.10.17
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