Transceiver Protocol Configurations In Cyclone V Devices; Pci Express - Altera Cyclone V Device Handbook

4-2

PCI Express

PCS Support
OBSAI
XAUI
Related Information
• Use this chapter along with the Altera Transceiver PHY IP Core User Guide.
• Upcoming Cyclone V Device Features
• Cyclone V Device Handbook: Known Issues
Lists the planned updates to the Cyclone V Device Handbook chapters.
PCI Express
The Cyclone Vdevices have PCIe Hard IP that is designed for performance, ease-of-use, and increased
functionality. The Hard IP consists of the media access control (MAC) lane, data link, and transaction layers.
The PCIe Hard IP supports the PCIe Gen1 end point and root port up to x4 lane configurations. The PCIe
endpoint support includes multifunction support for up to eight functions and Gen2 x4 lane configurations.
Figure 4-1: PCIe Multifunction for Cyclone V Devices
External System
The Cyclone V PCIe Hard IP operates independently from the core logic, which allows the PCIe link to
wake up and complete link training in less than 100 ms while the Cyclone V device completes loading the
programming file for the rest of the device.
In addition, the Cyclone V device PCIe Hard IP has improved end-to-end datapath protection using error
correction code (ECC).
Altera Corporation
Data Rates (Gbps)
0.768, 1.536, 3.072
3.125
Host CPU
Root
Complex
Local Local
Peripheral 1 Peripheral 2
Transmitter Datapath
The same as custom
single- and double-
width modes, plus the
TX deterministic
latency
Implemented using
soft PCS
FPGA Device
PCIe Link

Transceiver Protocol Configurations in Cyclone V Devices

Receiver Datapath
The same as custom single-
and double-width modes, plus
the RX deterministic latency
Implemented using soft PCS
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2013.10.17