Functional Description Of The Fpga Manager; Fpga Manager Building Blocks - Altera Cyclone V Device Handbook

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2013.12.30

Functional Description of the FPGA Manager

FPGA Manager Building Blocks

The FPGA manager has the two blocks (fabric I/O, monitor) to monitor the signals coming from the FPGA
portion of the device.
Fabric I/O
The fabric I/O block contains the following registers to allow simple low-latency communication between
the HPS and the FPGA fabric:
• General-purpose input register (gpi)
• General-purpose output register (gpo)
• Boot handshaking input register (misci)
These registers are only valid when the FPGA is in user mode. Reading from these registers while the FPGA
is not in user mode provides undefined data.
The 32 general-purpose input signals from the FPGA fabric are read by reading the gpi register using the
register slave interface. The 32 general-purpose output signals to the FPGA fabric are generated from writes
to the gpo register. For more information about FPGA manager registers, refer to "FPGA Manager Address
Map and Register Definitions."
The boot handshaking input signals from the FPGA fabric are read by reading the misci register. The
f2h_boot_from_fpga_ready signal indicates to the boot ROM when logic in the FPGA fabric is ready
to accept configuration interface requests from the HPS-to-FPGA bridge when the boot ROM is booting
from the FPGA. The f2h_boot_from_fpga_on_failure signal serves as a fallback in the event that
the boot ROM code fails to boot from the primary boot flash device. In this case, the boot ROM code checks
these two handshaking signals to determine if it should use the boot code hosted in the FPGA memory as
the next stage in the boot process.
There is no interrupt support for this block.
Monitor
The monitor block is an instance of the Synopsys
separate instance of the IP that comprises the three HPS GPIO interfaces. The monitor block connects to
the configuration signals in the FPGA. This block monitors key signals related to FPGA configuration such
as INIT_DON E, CRC_ERROR, and PR_DONE. Software configures the monitor block through the register
slave interface, and can either poll FPGA signals or be interrupted. The mon address map within the FPGA
manager register address map contains the monitor registers. For more information about FPGA manager
registers, refer to "FPGA Manager Address Map and Register Definitions."
You can program the FPGA manager to treat any of the monitor signals as interrupt sources. Independent
of the interrupt source type, the monitor block always drives an active-high level interrupt to the MPU. Each
interrupt source can be of the following types:
• Active-high level
• Active-low level
• Rising edge
• Falling edge
Note: Portions
are registered trademarks of Synopsys, Inc. All documentation is provided "as is" and without any
FPGA Manager
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Functional Description of the FPGA Manager
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DesignWare GPIO IP (DW_apb_gpio), which is a
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