Altera Cyclone V Device Handbook page 893

17-44
Receive Descriptor Field 0 (RDES0)
Bit
29:16 FL: Frame Length
These bits indicate the byte length of the received frame that was transferred to host memory
(including CRC). This field is valid when Last Descriptor (RDES0[8]) is set and either the
Descriptor Error (RDES0[14]) or Overflow Error bits are reset. The frame length also
includes the two bytes appended to the Ethernet frame when IP checksum calculation (Type
1) is enabled and the received frame is not a MAC control frame.
This field is valid when Last Descriptor (RDES0[8]) is set. When the Last Descriptor and
Error Summary bits are not set, this field indicates the accumulated number of bytes that
have been transferred for the current frame.
15 ES: Error Summary
Indicates the logical OR of the following bits:
• RDES0[1]: CRC Error
• RDES0[3]: Receive Error
• RDES0[4]: Watchdog Timeout
• RDES0[6]: Late Collision
• RDES0[7]: Giant Frame
• RDES4[4:3]: IP Header or Payload Error (Receive Descriptor Field 4 (RDES4))
• RDES0[11]: Overflow Error
• RDES0[14]: Descriptor Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.
14 DE: Descriptor Error
When set, this bit indicates a frame truncation caused by a frame that does not fit within
the current descriptor buffers, and that the DMA does not own the Next descriptor. The
frame is truncated. This field is valid only when the Last Descriptor (RDES0[8]) is set.
13 SAF: Source Address Filter Fail
When set, this bit indicates that the SA field of frame failed the SA Filter in the MAC.
12 LE: Length Error
When set, this bit indicates that the actual length of the frame received and that the Length/
Type field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is
reset.
11 OE: Overflow Error
When set, this bit indicates that the received frame was damaged because of buffer overflow
in MTL.
Note: This bit is set only when the DMA transfers a partial frame to the application. This
happens only when the RX FIFO buffer is operating in the threshold mode. In the store-
and-forward mode, all partial frames are dropped completely in RX FIFO buffer.
Altera Corporation
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Description
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Ethernet Media Access Controller
cv_54017
2013.12.30
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