Altera Cyclone V Device Handbook page 557

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2013.12.30
The HPS Peripherals Region
The HPS peripherals region is the top 64 MB in the address space, starting at 0xFC000000 and extending
to 0xFFFFFFFF. The HPS peripherals region is always allocated to the HPS dedicated peripherals for the
Altera Cortex-A9 MPU subsystem.
Performance Monitoring Unit
Each Cortex-A9 processor has a Performance Monitoring Unit (PMU). The PMU supports 58 events to
gather statistics on the operation of the processor and memory system. Six counters in the PMU accumulate
the events in real time. The PMU counters are accessible either from the processor itself, using the Coprocessor
14 (CP14) interface, or from an external debugger. The events are also supplied to the PTM and can be used
for trigger or trace.
For more information about the PMU, refer to the Performance Monitoring Unit chapter of the Cortex-A9
Technical Reference Manual, available on the ARM website (infocenter.arm.com).
Related Information
ARM Infocenter (www.infocenter.arm.com)
MPCore Timers
There is one interval timer and one watchdog timer for each processor.
Functional Description
Each timer is private, meaning that only its associated processor can access it. If the watchdog timer is not
needed, it can be configured as a second interval timer.
Each private interval and watchdog timer has the following features:
• A 32-bit counter that optionally generates an interrupt when it reaches zero
• Configurable starting values for the counter
• An eight-bit prescaler value to qualify the clock period
Implementation Details
The timers are configurable to either single-shot or auto-reload mode. The timer blocks are clocked by
mpu_periph_clk, running at ¼ the rate of mpu_clk.
For more information about private timers, refer to "About the private timer and watchdog blocks" in the
Global timer, Private timers, and Watchdog registers chapter of the Cortex-A9 MPCore Technical Reference
Manual, available on the ARM website (infocenter.arm.com).
Related Information
ARM Infocenter (www.infocenter.arm.com)
Generic Interrupt Controller
Functional Description
The Generic Interrupt Controller (GIC) supports up to 180 interrupt sources, including dedicated peripherals
and IP implemented in the FPGA fabric. In a dual-core system, the GIC is shared by both Cortex-A9
processors. Each processor also has 16 banked software-generated interrupts and 16 banked private peripheral
interrupts.
Cortex-A9 Microprocessor Unit Subsystem
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The HPS Peripherals Region
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