Slave Spi And Ssp Serial Transfers - Altera Cyclone V Device Handbook

19-22

Slave SPI and SSP Serial Transfers

6. The shift control logic stops the transfer when the transmit FIFO buffer is empty. If the transfer mode is
sequential and the SPI master receives data, the shift control logic stops the transfer when the specified
number of data frames is received. When the transfer is done, the BUSY status is reset to 0.
7. If the SPI master receives data, read the receive FIFO buffer until it is empty.
8. Disable the SPI master by writing 0 to SSIENR.
Slave SPI and SSP Serial Transfers
Figure 19-13: Slave SPI or SSP Serial Transfer Software Flow
Altera Corporation
Idle
Disable SPI
Configure Slave by Writing
CTRLR0, CTRLR1, TXFTLR,
RXFTLR, MWCR, & IMR
Enable SPI
Write Data
to Tx FIFO
TMOD = 10
Wait for Master
to Select Slave
Transfer
in Progress
yes
Interrupt Service
Interrupt?
If the transmit FIFO makes the request
no
and all data has not been sent, write
data to the transmit FIFO.
If the receive FIFO makes the request,
read data from the receive FIFO.
Busy?
yes
no
Read Rx
FIFO
Routine
TMOD = 01
cv_54019
2013.12.30
SPI Controller
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