Altera Cyclone V Device Handbook page 341

CV-53002
2013.05.06
Figure 2-2: Input Reference Clock Sources for Transceiver Channels
GXB_L1
GXB_L0
Related Information
Cyclone V Device Datasheet
Dedicated refclk Using the Reference Clock Network
Designs that use multiple channel PLLs with the same clock frequency can use the same dedicated refclk
pin. Each dedicated refclk pin can drive any channel PLL (CMU PLL/CDR) and the fractional PLL
through the reference clock network.
Figure 2-2
six transceiver channels, the total number of clock lines in the reference clock network is 2 (N = 6/3).
Dual-Purpose RX/refclk Pins
When not used as a receiver, an RX differential pair can be used as an additional input reference clock source.
The clock from the RX pins feed the RX clock network that spans all the channels on one side of the device.
Only one RX differential pair for every three channels can be used as input reference clock at a time. The
following figure shows the use of dual-purpose RX/refclk differential pin as input reference clock source
and the RX clock network.
Transceiver Clocking in Cyclone V Devices
Send Feedback
Dedicated
refclk
Transmitter
Transceiver
Channel 5
Receiver
Transmitter
Transceiver
Channel 4
Receiver
Transmitter
Transceiver
Channel 3
Receiver
Dedicated
refclk
Transmitter
Transceiver
Channel 2
Receiver
Transmitter
Transceiver
Channel 1
Receiver
Transmitter
Transceiver
Channel 0
Receiver
Note (1):
N is the number of dedicated refclk pins, which equals the number of transceiver channels on a side divided by 3.
shows the input reference clock sources for six channel PLLs across two transceiver banks. For
Dedicated refclk Using the Reference Clock Network
Channel PLL
Channel PLL
Channel PLL
Channel PLL
Channel PLL
Channel PLL
Reference Clock
Network
N
N
N
N
N
N
N (1)
Altera Corporation
2-3