Altera Cyclone V Device Handbook page 415

CV-53004
2013.10.17
pattern (K28.5). User logic is not required to manipulate the TX bit slipper for constant round-trip delay.
In manual mode, the TX bit slipper is able to compensate one unit interval (UI).
The word alignment pattern (K28.5) position varies in byte deserialized data. Delay variation is up to ½
parallel clock cycle. You must add in extra user logic to manually check the K28.5 position in byte deserialized
data for the actual latency.
Figure 4-32: Deterministic Latency State Machine in the Word Aligner
Table 4-11: Methods to Achieve Deterministic Latency Mode in Cyclone V Devices
Description
Manual alignment with bit
position indicator provides
deterministic latency. Delay
variation up to 1 parallel clock
cycle
Related Information
Refer to the "Deterministic Latency PHY IP Core" chapter in the Altera Transceiver PHY IP Core User
Guide
(14)
Enhanced deterministic latency feature in Cyclone V devices.
Transceiver Protocol Configurations in Cyclone V Devices
Send Feedback
To 8B/10B Decoder Deterministic Latency
Synchronization State Machine
Existing Feature
Requirement
Extra user logic to
manipulate the TX bit
slipper with a bit
position indicator
from the word aligner
for constant total
round-trip delay
Clock-slip Control
Word Aligner
Description
Deterministic latency
state machine
alignment reduces the
known delay variation
in word alignment
operation
CPRI Enhancements
From RX CDR
Deserializer
(14)
Enhanced Feature
Requirement
None
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