Altera Cyclone V Device Handbook page 542

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2013.12.30
The GPV allows you to set the bridge's issuing capabilities to support single or multiple transactions. The
GPV also lets you set a write tidemark through the wr_tidemark register, to control how much data is
buffered in the bridge before data is written to slaves in the FPGA fabric.
Note: It is critical to provide correct clock settings for the lightweight HPS-to-FPGA bridge, even if your
design does not use this bridge. The l4_mp_clk clock is required for GPV access on the HPS-to-
FPGA and FPGA-to-HPS bridges.
Related Information
• AXI Bridges Block Diagram and System Integration
• The Global Programmers View
Lightweight HPS-to-FPGA Bridge Master Signals
All the lightweight HPS-to-FPGA bridge master signals have a fixed width. The following tables list all the
signals exposed by the lightweight HPS-to-FPGA master interface to the FPGA fabric.
Table 5-16: Lightweight HPS-to-FPGA Bridge Master Write Address Channel Signals
Signal
AWID
AWADDR
AWLEN
AWSIZE
AWBURST
AWLOCK
AWCACHE
AWPROT
AWVALID
AWREADY
Table 5-17: Lightweight HPS-to-FPGA Bridge Master Write Data Channel Signals
Signal
WID
WDATA
WSTRB
WLAST
HPS-FPGA AXI Bridges
Send Feedback
Width Direction
12 bits Output
21 bits Output
4 bits Output
3 bits Output
2 bits Output
2 bits Output
4 bits Output
3 bits Output
1 bit Output
1 bit Input
Width Direction
12 bits Output
32 bits Output
4 bits Output
1 bit Output
Lightweight HPS-to-FPGA Bridge Master Signals
on page 5-3
Write address ID
Write address
Burst length
Burst size
Burst type
Lock type Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Write address channel valid
Write address channel ready
Write ID
Write data
Write data strobes
Write last data identifier
Description
Description
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