Arm Coresight Documentation - Altera Cyclone V Device Handbook

7-2

ARM CoreSight Documentation

• Capability to route trace data to any slave accessible to the ETR AXI master connected to the level 3 (L3)
interconnect
• Capability for the following SoC modules to trigger each other through the embedded cross-trigger
system:
• FPGA fabric
• A9-0 processor
• A9-1 processor
• PTM-0
• PTM-1
• STM
• ETF
• ETR
• TPIU
• csCTI
• CTI-0
• CTI-1
• FPGA-CTI
• csCTM
• CTM
ARM CoreSight Documentation
The following ARM CoreSight specifications and documentation provide a more thorough description of
the ARM CoreSight components in the HPS debug system:
• CoreSight Technology, System Design Guide, ARM DGI 0012D
• CoreSight Architecture Specification, ARM IHI 0029B
• ARM Debug Interface v5, Architecture Specification, ARM IHI 0031A
• Embedded Cross Trigger Technical Reference Manual, ARM DDI 0291A
• CoreSight Components Technical Reference Manual, ARM DDI 0314H
• CoreSight Program Flow Trace, Architecture Specification, ARM IHI 0035A
• CoreSight PTM-A9 Technical Reference Manual, ARM DDI 0401B
• CoreSight System Trace Macrocell Technical Reference Manual, ARM DDI 0444A
• System Trace Macrocell, Programmers' Model Architecture Specification, ARM IHI 0054
• CoreSight Trace Memory Controller Technical Reference Manual, ARM DDI 0461B
Related Information
Info center
For more information, refer to the CoreSight Components Technical Reference Manual and the CoreSight
Technology System Design Guide.
Altera Corporation
cv_54007
2013.12.30
CoreSight Debug and Trace
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