Dma Peripheral Request Controller - Altera Cyclone V Device Handbook

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2013.12.30
of entries reserved for indirect read operations. For example, write the value 32 (0x20) to partition the 128-
entry SRAM to 32 entries (25%) for read usage and 96 entries (75%) for write usage.
For more information about ECC, refer to the System Manager chapter in volume 3 of the Cyclone
Handbook.
Related Information
System Manager

DMA Peripheral Request Controller

The DMA peripheral request controller is only used for the indirect mode of operation where data is
temporarily stored in the SRAM. The quad SPI flash controller uses the DMA peripheral request interface
to trigger the external DMA into performing data transfers between memory and the quad SPI controller.
There are two DMA peripheral request interfaces, one for indirect reads and one for indirect writes. The
DMA peripheral request controller can issue two types of DMA requests, single or burst, to the external
DMA. The number of bytes for each single or burst request is specified in the number of single bytes
(numsglreqbytes) and number of burst bytes (numburstreqbytes) fields of the DMA peripheral
register (dmaper). The DMA peripheral request controller splits the total amount of data to be transferred
into a number of DMA burst and single requests by dividing the total number of bytes by the number of
bytes specified in the burst request, and then dividing the remainder by the number of bytes in a single
request.
Note: When programming the DMA controller, the burst request size must match the burst request size
set in the quad SPI controller to avoid quickly reaching an overflow or underflow condition.
For indirect reads, the DMA peripheral request controller only issues DMA requests after the data has been
retrieved from flash memory and written to SRAM. The rate at which DMA requests are issued depends on
the watermark level. The indrdwater register defines the minimum fill level in bytes at which the DMA
peripheral request controller can issue the DMA request. The higher this number is, the more data that must
be buffered in SRAM before the external DMA moves the data. When the SRAM fill level passes the watermark
level, the transfer watermark reached interrupt is generated.
For example, consider the following conditions:
• The total amount of data to be read using indirect mode is 256 bytes
• The SRAM watermark level is set at 128 bytes
• Software configures the burst type transfer size to 64 bytes
Under these conditions, the DMA peripheral request controller issues the first DMA burst request when the
SRAM fill level passes 128 bytes (the watermark level). The DMA peripheral request controller triggers
consecutive DMA burst requests as long as there is sufficient data in the SRAM to perform burst type requests.
In this example, DMA peripheral request controller can issue at least two consecutive DMA burst requests
to transfer a total of 128 bytes. If there is sufficient data in the SRAM, the DMA peripheral request controller
requests the third DMA burst immediately. Otherwise the DMA peripheral request controller waits for the
SRAM fill level to pass the watermark level again to trigger the next burst request. When the watermark level
is triggered, there is sufficient data in the SRAM to perform the third and fourth burst requests to complete
the entire transaction.
For the indirect writes, the DMA peripheral request controller issues DMA requests immediately after the
transfer is triggered and continues to do so until the entire indirect write transfer has been transferred. The
rate at which DMA requests are issued depends on the watermark level. The indwrwater register defines
the maximum fill level in bytes at which the controller can issue the first DMA burst or single request. When
the SRAM fill level falls below the watermark level, the transfer watermark reached interrupt is generated.
Quad SPI Flash Controller
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DMA Peripheral Request Controller
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