Altera Cyclone V Device Handbook page 977

21-4
Automatic RTS mode
Automatic RTS mode
Automatic RTS mode becomes active when the following conditions occur: †
• RTS (MCR.RTS bit and MCR.AFCE bit are both set)
• FIFO buffers are enabled (IIR_FCR.FIFOE bit is set)
When automatic RTS is enabled, the rts_n output pin is forced inactive (high) when the receive FIFO
buffer level reaches the threshold set by RCVR trigger (IIR_FCR.RT). When rts_n is connected to the
cts_n input pin of another UART device, the other UART stops sending serial data until the receive FIFO
buffer has available space (until it is completely empty). †
The selectable receive FIFO buffer threshold values are 1, ¼, ½, and 2 less than full. Because one additional
character may be transmitted to the UART after rts_n is inactive (due to data already having entered the
transmitter block in the other UART), setting the threshold to 2 less than full allows maximum use of the
FIFO buffer with a margin of one character. †
Once the receive FIFO buffer is completely emptied by reading the receiver buffer register (RBR_THR_DLL),
rts_n again becomes active (low), signalling the other UART to continue sending data.†
Even when you set the correct MCR bits, if the FIFO buffers are disabled through FCR.FIFOE, automatic
flow control is also disabled. When auto RTS is not implemented or disabled, rts_n is controlled solely by
MCR.RTS. In the Automatic RTS Timing diagram, the character T is received because rts_n is not detected
prior to the next character entering the sending UART transmitter. †
Figure 21-2: Automatic RTS Timing
Automatic CTS mode
Automatic CTS mode becomes active when the following conditions occur: †
• AFCE (MCR.AFCE bit is set)
• FIFO buffers are enabled (through FIFO buffer control register IIR_FCR.FIFOE) bit
When automatic CTS is enabled (active), the UART transmitter is disabled whenever the cts_n input
becomes inactive (high). This prevents overflowing the FIFO buffer of the receiving UART. †
If the cts_n input is not deactivated before the middle of the last stop bit, another character is transmitted
before the transmitter is disabled. While the transmitter is disabled, you can continue to write and even
overflow to the transmit FIFO buffer. †
Automatic CTS mode requires the following sequence:
1. The UART status register are read to verify that the transmit FIFO buffer is full (UART status register
USR.TFNF set to zero). †
2. The current FIFO buffer level is read via the transmit FIFO level (TFL) register. †
3. Programmable THRE interrupt mode must be enabled to access the FIFO buffer full status from the LSR.
†
When using the FIFO buffer full status, software can poll this before each write to the transmit FIFO buffer.
When the cts_n input becomes active (low) again, transmission resumes. If the FIFO buffers are disabled
Altera Corporation
sin
start character T
rts_n
rx_fifo_read
stop start character T+1 stop
1 2 3 T T+1
UART Controller
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cv_54021
2013.12.30