Forward Parallel Loopback - Altera Cyclone V Device Handbook

6-2

Forward Parallel Loopback

The looped-back data is forwarded to the receiver clock data recovery (CDR). You must provide an alignment
pattern for the word aligner to enable the receiver channel to retrieve the byte boundary.
If the device is not in the serial loopback configuration and is receiving data from a remote device, the
recovered clock from the receiver CDR is locked to the data from the remote source.
Note: For the phy_serial_loopback register access description and addressing, refer to the "Loopback
Modes" section of the Transceiver Reconfiguration Controller chapter in the Altera Transceiver PHY
IP Core User Guide.
If the device is placed in the serial loopback configuration, the data source to the receiver changes from the
remote device to the local transmitter channel—prompting the receiver CDR to start tracking the phase of
the new data source. During this time, the recovered clock from the receiver CDR may be unstable. Because
the receiver PCS is running off of this recovered clock, you must place the receiver PCS under reset by
asserting the rx_digitalreset signal during this period.
Note:
When moving into or out of serial loopback, you must assert the rx_digitalreset signal for a
minimum of two parallel clock cycles.
Related Information
Altera Transceiver PHY IP Core User Guide
Forward Parallel Loopback
Forward parallel loopback is a debugging aid to ensure the enabled PCS blocks in the transmitter and receiver
channel function correctly.
Forward parallel loopback is only available in transceiver Native PHY. You enable forward parallel loopback
by enabling the PRBS test mode, through the dynamic reconfiguration controller. You must perform a
rx_digitalreset after the dynamic reconfiguration operation has completed.
Parallel data travels across the forward parallel loopback path, passing through the RX word aligner, and
finally verified inside the RX PCS PRBS verifier block. Check the operations status from the FPGA fabric.
Figure 6-2: Parallel Loopback Datapath
The following figure shows the parallel PRBS data generated by the TX PCS PRBS generator block.
Transmitter PMA
Receiver PMA
Note: Usage details for the feature are described in the Altera Transceiver PHY IP Core User Guide.
Altera Corporation
Transmitter PCS
Forward Parallel
Loopback Path
PRBS Gen
Receiver PCS
PRBS
Checker
CV-53006
2013.05.06
FPGA
Fabric
Transceiver Loopback Support
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