Altera Cyclone V Device Handbook page 558

6-12
Implementation Details
Implementation Details
The configuration and control for the GIC is memory-mapped and accessed through the SCU. The GIC are
clocked by mpu_periph_clk, running at ¼ the rate of mpu_clk.
For more information about the GIC, refer to the Interrupt Controller chapter of the Cortex-A9 MPCore
Technical Reference Manual, available on the ARM website (infocenter.arm.com).
Related Information
• GIC Interrupt Map for the Cyclone V SoC HPS
The following table shows the interrupt map.
• ARM Infocenter (www.infocenter.arm.com)
GIC Interrupt Map for the Cyclone V SoC HPS
The following table shows the interrupt map.
Table 6-2: GIC Interrupt Map
GIC Source Block
Interrupt
Number
(6)
32 CortexA9_0
33 CortexA9_0
34 CortexA9_0
35 CortexA9_0
36 CortexA9_0
37 CortexA9_0
38 CortexA9_0
39 CortexA9_0
40 CortexA9_0
41 CortexA9_0
42 CortexA9_0
43 CortexA9_0
44 CortexA9_0
(6)
To ensure that you are using the correct GIC interrupt number, your code should refer to the symbolic interrupt
name, as shown in the Interrupt Name column. Symbolic interrupt names are defined in a header file distributed
with the source installation for your operating system.
(7)
This interrupt combines the interrupts named cpu0_parityfail_*.
Altera Corporation
Interrupt Name
cpu0_parityfail
cpu0_parityfail_BTAC
cpu0_parityfail_GHB
cpu0_parityfail_I_Tag
cpu0_parityfail_I_Data
cpu0_parityfail_TLB
cpu0_parityfail_D_Outer
cpu0_parityfail_D_Tag
cpu0_parityfail_D_Data
cpu0_deflags0
cpu0_deflags1
cpu0_deflags2
cpu0_deflags3
on page 6-12
Combined
Interrupts
(7)
Cortex-A9 Microprocessor Unit Subsystem
cv_54006
2013.12.30
Triggering
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Level
Level
Level
Level
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