Altera Cyclone V Device Handbook page 310

CV-53001
2013.05.06
After switching to LTD mode, the rx_is_lockedtodata status signal is asserted. Lock to data takes a
minimum of 4 μs, however the actual lock time depends on the transition density of the incoming data and
the parts per million (PPM) difference between the receiver input reference clock and the upstream transmitter
reference clock. The receiver PCS logic must be held in reset until the CDR produces a stable recovered
clock.
If there is no transition on the incoming serial data for an extended duration, the CDR output clock may
drift to a frequency exceeding the configured PPM threshold when compared with the input reference clock.
In such a case, the LTR/LTD controller transitions the CDR PLL from LTD to LTR mode.
CDR PLL in Manual Lock Mode
In manual lock mode, the LTR/LTD controller directs the transition between the LTR and LTD modes based
on user-controlled settings in the pma_rx_set_locktodata and pma_rx_set_locktoref registers.
Alternatively you can control it using the rx_set_locktodata and rx_set_locktoref ports
available in the transceiver PHY IPs.
In LTR mode, the phase detector is not active. When the CDR PLL locks to the input reference clock, you
can switch the CDR PLL to LTD mode to recover the clock and data from the incoming serial data.
In LTD mode, the PFD output is not valid and may cause the lock detect status indicator to toggle randomly.
When there is no transition on the incoming serial data for an extended duration, you must switch the CDR
PLL to LTR mode to wait for the read serial data.
Manual lock mode provides the flexibility to manually control the CDR PLL mode transitions bypassing the
PPM detection as required by certain applications that include, but not limited to, the following:
• Link with frequency differences between the upstream transmitter and the local receiver clocks exceeding
the CDR PLL ppm threshold detection capability. For example, a system with asynchronous spread-
spectrum clocking (SSC) downspread of 0.5% where the SSC modulation results in a PPM difference
of up to 5000.
• Link that requires a faster CDR PLL transition to LTD mode, avoiding the duration incurred by the PPM
detection in automatic lock mode.
In manual lock mode, your design must include a mechanism—similar to a PPM detector—that ensures the
CDR PLL output clock is kept close to the optimum recovered clock rate before recovering the clock and
data. Otherwise, the CDR PLL might not achieve locking to data. If the CDR PLL output clock frequency is
detected as not close to the optimum recovered clock rate in LTD mode, direct the CDR PLL to LTR mode.
Related Information
Transceiver Reset Control and Power Down in Cyclone V Devices
Channel PLL as a CMU PLL
When you use the channel PLL as the CMU PLL, you can configure the transceiver channel only as a
transmitter.
The CMU PLL operates in LTR mode only and supports the full range of data rates.
The VCO of the PLL operates at half rate and the L-counter dividers (PFD), after the VCO, extend the PLL
data rate range.
Note: CDR functionality for the receiver is not available when you configure the channel PLL as a CMU
PLL—you can use the transceiver channel only as a transmitter.
Transceiver Architecture in Cyclone V Devices
Send Feedback
CDR PLL in Manual Lock Mode
Altera Corporation
1-23