Altera Cyclone V Device Handbook page 684

11-6
Interrupt Controller Unit
Interrupt Controller Unit
The interrupt controller unit generates an interrupt that depends on the rintsts register, the interrupt
mask register (intmask), and the interrupt enable bit (int_enable) of the control register (ctrl).
Once an interrupt condition is detected, the controller sets the corresponding interrupt bit in the rintsts
register. The bit in the rintsts register remains set to 1 until the software resets the bit to 0 by writing a
1 to the interrupt bit; writing a 0 leaves the bit untouched.
The interrupt port is an active-high, level-sensitive interrupt. The interrupt port is active only when at least
one bit in the rintsts register is set to 1, the corresponding intmask register bit is 1, and the
int_enable bit of the ctrl register is 1.
The following conditions can cause the interrupt to occur:
• End-bit error on read
• No cyclic redundancy code (CRC) on write
• Auto command done
• Start-bit error
• Hardware locked write error
• FIFO buffer underflow or overflow error
• Data starvation by host timeout
• Data read timeout or boot data start
• Response timeout or boot ACK received
• Data CRC error
• Response CRC error
• Receive FIFO buffer data request
• Transmit FIFO buffer data request
• Data transfer over
• Command done
• Response error
The int_enable bit of the ctrl register is set to 0 on power-on, and the intmask register bits are set
to 0x0000000, which masks all the interrupts.
Interrupt Setting and Clearing
The Receive FIFO Data Request and Transmit FIFO Data Request interrupts are set by level-sensitive interrupt
sources. Therefore, the interrupt source must be first cleared before you can reset the interrupt's corresponding
bit in the rintsts register to 0.
For example, on receiving the Receive FIFO Data Request interrupt, the FIFO buffer must be emptied so
that the FIFO buffer count is not greater than the RX watermark, which causes the interrupt to be triggered.
The rest of the interrupts are triggered by single clock-pulse-width sources.
FIFO Buffer
The SD/MMC controller has a 4 KB data FIFO buffer for storing transmit and receive data. The FIFO buffer
memory supports error correction codes (ECCs). Both interfaces to the FIFO buffer support single and
double bit error injection. The enable and error injection pins are inputs driven by the system manager and
the status pins are outputs driven to the MPU subsystem.
Altera Corporation
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SD/MMC Controller
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2013.12.30
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