Altera Cyclone V Device Handbook page 320

CV-53001
2013.05.06
Figure 1-27: 8B/10B Encoder Output During and After Reset Conditions
8B/10B encoder output during and after reset conditions in both single- and double-width modes.
(a) Single-Width Mode
tx_digitalreset
(b) Double-Width Mode
tx_digitalreset
dataout[19:10]
Table 1-14: 8B/10B Encoder Output During and After Reset Conditions
Operation Mode
Single Width
Double Width
Transmitter Bit-Slip
The transmitter bit-slip allows you to compensate for the channel-to-channel skew between multiple
transmitter channels by slipping the data sent to the PMA. The maximum number of bits slipped is controlled
from the FPGA fabric and is equal to the width of the PMA-PCS minus 1.
Transceiver Architecture in Cyclone V Devices
Send Feedback
clock
dataout[9:0] K28.5- K28.5-
clock
K28.5+ K28.5+
dataout[9:0] K28.5- K28.5-
During 8B/10B Reset
Continuously sends the /K28.5/ code from
the RD column
Continuously sends the /K28.5/ code from
the RD column on the LSByte and the /
K28.5/ code from the RD+ column on the
MSByte
K28.5- XXX XXX XXX
K28.5+ XXX XXX XXX
K28.5- XXX XXX XXX
Some "don't cares" are seen due to pipelining
in the transmitter channel, followed by three
/K28.5/ codes with proper disparity—starts
with negative disparity—before sending
encoded 8-bit data at its input.
Some "don't cares" are seen due to pipelining
in the transmitter channel, followed by:
• Three /K28.5/ codes from the RD
• Three /K28.5/ codes from the RD+
Transmitter Bit-Slip
K28.5- K28.5+ K28.5-
K28.5+ K28.5+ K28.5+
K28.5- K28.5- K28.5-
After 8B/10B Reset Release
column before sending encoded 8-bit
data at its input on LSByte.
column before sending encoded 8-bit
data at its input on MSByte.
1-33
Dx.y+
Dx.y+
Dx.y-
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