Altera Cyclone V Device Handbook page 329

1-42
Receiver Byte Reversal
Bit Reversal Option
Enabled
Note: When receiving the MSB-to-LSB transmission, the word aligner receives the data in reverse order.
The word alignment pattern must be reversed accordingly to match the MSB first incoming data
ordering.
You can dynamically control the bit reversal feature to use the rx_bitreversal_enable register with
the word aligner in bit-slip mode. When you dynamically enable the bit reversal feature in bit-slip mode,
ignore the pattern detection function in the word aligner because the word alignment pattern cannot be
dynamically reversed to match the MSB first incoming data order.
Receiver Byte Reversal
In double-width mode, two symbols of incoming data at the receiver may be accidentally swapped during
transmission. For a 16-bit input data width at the word aligner, the two symbols are bits[15:8] and
bits[7:0]. For a 20-bit input data width at the word aligner, the two symbols are bits[19:10] and
bits[9:0]. The byte reversal feature at the word aligner output corrects the swapped signal error by swapping
the two symbols in double-width mode at the word aligner output, as listed in
Table 1-26: Byte Reversal Feature
Byte Reversal Option
Disabled
Enabled
The reversal is controlled dynamically using the rx_bytereversal_enable register, and when you
enable the receiver byte reversal option, this may cause initial disparity errors at the receiver with 8B/10B-
coded data. The receiver must be able to tolerate these disparity errors.
Note: When receiving swapped symbols, the word alignment pattern must be byte-reversed accordingly
to match the incoming byte-reversed data.
Rate Match FIFO
The Rate Match FIFO compensates for the small clock frequency differences between the upstream transmitter
and the local receiver clocks.
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Single-Width Mode (8 or 10 bit)
MSB to LSB
For example:
8-bit—D[7:0] rewired
to D[0:7]
10-bit—D[9:0] rewired
to D[0:9]
16-bit Data Width
D[15:0]
D[7:0], D[15:8]
Received Bit Order
Double-Width Mode (16 or 20 bit)
MSB to LSB
For example:
16-bit—D[15:0] rewired to D[0:15]
20-bit—D[19:0] rewired to D[0:19]
Word Aligner Output
20-bit Data Width
D[19:0]
D[9:0], D[19:10]
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
Table 1-26.
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