Multi-Port Front End - Altera Cyclone V Device Handbook

cv_54008
2013.12.30
Figure 8-2: SDRAM Controller Block Diagram
FPGA
Fabric

Multi-Port Front End

The Multi-Port Front End (MPFE) is responsible for scheduling pending transactions from the configured
interfaces and sending the scheduled memory transactions to the single-port controller. The MPFE handles
all functions related to individual ports.
The MPFE consists of three primary sub-blocks, which are described below.
Command Block
The command block accepts read and write transactions from the FPGA fabric and the HPS. When the
command FIFO buffer is full, the command block applies backpressure by deasserting the ready signal. For
each pending transaction, the command block calculates the next SDRAM burst needed to progress on that
transaction. The command block schedules pending SDRAM burst commands based on the user-supplied
configuration, available write data, and unallocated read data space.
Write Data Block
The write data block transmits data to the single-port controller. The write data block maintains write data
FIFO buffers and clock boundary crossing for the write data. The write data block informs the command
block of the amount of pending write data for each transaction so that the command block can calculate
eligibility for the next SDRAM write burst.
SDRAM Controller Subsystem
Send Feedback
Multi-Port Front End
Read Data
6
Data
Reorder
FIFO
Buffer
Buffers
Write Data
6
FIFO
Data
POP
FIFO
Logic
Buffers
Command
6 Write
WR Acknowledge
Acknowledge Queues
10
Command
Scheduler
FIFO
Buffers
Control & Status Register Interface
SDRAM Controller
Single-Port Controller
Write Data
Buffer
Timer
Command
Bank
Generator
Pool
Multi-Port Front End
ECC
Generation
&
Checking
Altera
PHY
Interface
Rank Timer
Arbiter
Altera Corporation
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